Projects Showcase
Here are some of the important academic projects I participated in and contributed to
A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo
October 2023 - April 2024
ETH Zurich, Zurich, Switzerland
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Designed custom RISC-V ISA extensions and microarchitectural enhancements for the Snitch core, optimizing it for high-efficiency multithreaded execution.
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Accelerated execution performance by 1.8X IPC and hit 90% FPU utilization by identifying and eliminating hardware bottlenecks.
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Programmed bare-metal Monte Carlo simulations using C and low-level RISC-V assembly to benchmark new instruction execution.
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Executed RTL verification and developed C-based testbenches to validate custom extension functionality.
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Built a GF12 topographical synthesis flow to conduct detailed Power, Performance, and Area (PPA) trade-off evaluations.
Figure: F. Zaruba, F. Schuiki, T. Hoefler, and L. Benini, "Snitch: A tiny pseudo dual-issue processor for area and energy efficient execution of floating-point intensive workloads," ACM Transactions on Architecture and Code Optimization, vol. 17, no. 1, pp. 1-25, 2020. doi: 10.1145/3386326.
Towards Open-Source: ASICs: Physical Implementation Gap-Analysis of a Linux-Capable SoC Vehicle in 130nm CMOS
February 2023 - June 2022
ETH Zurich, Zurich, Switzerland
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Engineered the physical backend design for the IHP 130nm Linux-capable SoC "Iguana."
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Advanced open-source EDA adoption by building a physical design flow based on the open IHP PDK and Yosys-synthesized netlists.
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Modified and enhanced custom standard cells in Cadence Virtuoso through participation in two competitive cell hackathons.
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Executed statistical benchmarks to rigorously evaluate and contrast distinct physical design implementation strategies.
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Co-piloted final chip preparation, delivering the clean GDSII tapeout files for the Iguana project
Figure: Die Size and Macro Orientation of Iguana
Figure: Final Look of Layout Sent to the Foundry
Investigation of the T-head Floating Point Division and Square Root Unit
February 2022 - May 2022
ETH Zurich, Zurich, Switzerland
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Integrated T-head’s floating point arithmetic module (32-bit) into the current FPU of ETH’s Pulpissimo microcontroller architecture
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Analyzed and compared the algorithms, latencies, performances, areas, and powers used in T-head’s FPU and Pulpissimo’s FPU
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Conducted a full chip design flow: a synthesis of the FPU and a back-end flow which includes floorplanning, place & route using TSMC 65nm technology.
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Conducted a technical presentation under the supervision of Prof. Luca Benini's Integrated Systems Laboratory (IIS)
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Prepared a professional report in Latex.
Figure: T-HEAD Xuantie E906
Photo adapted from https://www.t-head.cn
Figure: FPU Top Level with subgroups
Photo adapted from presentation, May 30th, 2021
Reference Links:
https://github.com/T-head-Semi/openc906
https://github.com/pulp-platform?q=cv&type=all&language=&sort=
Implementation and Overhead Analysis of an OpenMP Kernel Based on Its Bare-metal Counterpart on Snitch
July 2023 - August 2023
ETH Zurich, Zurich, Switzerland
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Port a bare-metal kernel application (already available on Snitch) to OpenMP using its compiler directives and runtime library
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Comparison runtime of OpenMP and bare-metal AXPY
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Investigate causes of overhead introduced by OpenMP
Reference Links:
https://github.com/pulp-platform/snitch_cluster
Independent Chip Testing: Kairos
July 2023
ETH Zurich, Zurich, Switzerland
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Collaborated with teammate to configure the basic setup for testing Kairos, a TSMC65 chip implementing a power controller for HPC systems, using automatic test equipment (ATE) available at IIS lab.
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Carried out the first successful continuity test, a functional test using test vectors generated using VCD method, as well as a JTAG minimal boost test.
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Profiled reference clock frequency and also collected static power measurements for the core and pads, dynamic power measurements for the core of the chip, namely Kairos.
Figure: Testflow Setup on ATE
Reference Links:
http://asic.ethz.ch/2022/Kairos.html
Bachelor’s Thesis-Intuitive Thrombectomy Control
September 2020 - March 2021
Worcester, MA, USA
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Conducted literature review regarding thrombectomy and available medical devices in targeting blood clots removal
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Evaluated the risks that surgeons face when doing a thrombectomy surgery.
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Collaboratively designed linear force feedback and torque force feedback mechanisms that allow a brain surgeon to perform remote surgery with standard guidewire manipulation techniques
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Installed controllers via coding with Arduino Mega 2560, which reads and processes the data of the haptic feedback mechanisms for post data processing
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Turned the controller via Arduino IDE
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Produced a professional report and delivered a final project presentation
Figure: Control Box of the Haptic Feedback System
Reference: Lu, Y., Litovchick, S., Batista, R., & Jiang, L. (2021). An Intuitive User Interface for Teleoperated Robotic Neuro-Intervention. : Worcester Polytechnic Institute.
NASA University Student Launch Initiative (USLI)
September 2018 - April 2019
Worcester, MA, USA
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Integrated Radio transceivers Adafruit RFM95W Lora
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Collaboratively designed PCB layout using Fritzing
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Conducted tests on the performances of transceivers
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Delivered PDR and CDR to NASA; rocket launched in Marshall Space Flight Center in Huntsville, Alabama
